1 of 21

111999

FEATURES

Integrated NV SRAM, real time clock, crystal,
power-fail control circuit and lithium energy
source

Clock registers are accessed identically to the
static RAM; these registers are resident in the
16 top RAM locations

Century byte register; i.e., Y2K complaint

Totally nonvolatile with over 10 years of
operation in the absence of power

Precision power-on reset

Programmable watchdog timer and RTC alarm

BCD coded year, month, date, day, hours,
minutes, and seconds with automatic leap year
compensation valid up to the year 2100

Battery voltage level indicator flag

Power-fail write protection allows for

�

10%

power supply tolerance

Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time

PIN ASSIGNMENT

DS1554

256K NV Y2KC Timekeeping RAM

PRELIMINARY

www.dalsemi.com

IRQ/FT

RST

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

GND

A14

A13

A12

A11

A10

X1 GND V

BAT

34-Pin POWERCAP MODULE BOARD

(USES DS9034PCX POWERCAP)

RST

1
2
3
4
5
6
7
8
9
10
11
12

A14

A5
A4
A3
A2
A1
A0

DQ1

DQ0

NC
IRQ/FT
WE
A13
A8
A9
A11
OE
A10
CE
DQ7

DQ5

DQ6

30
29
28
27
26
25
24
23
22
21

A16

A12

DQ2

GND

15
16

18
17

DQ4
DQ3

32-PIN ENCAPSULATED PACKAGE

DS1554

2 of 21

ORDERING INFORMATION

DS1554P-XXX

(5-Volt)
-70

70 ns access

-100 100 ns access

blank 32-pin DIP Module
P

34-pin PowerCap Module

board*

*DS1554WP-XXX

(3.3 Volt)
-120 120 ns access
-150

150 ns access

blank 32-pin DIP Module
P

34-pin PowerCap Module
board*

*DS9034PCX (PowerCap) Required:

must be ordered seperately

PIN DESCRIPTION

A0-A14 -

Address

Input

DQ0-DQ7 -

Data

Input/Outputs

IRQ

\FT

- Interrupt, Frequency Test Output
(Open Drain)

RST

- Power-On Reset Output
(Open Drain)

- Chip Enable

- Output Enable

- Write Enable

- Power Supply Input

GND -

Ground

- No Connection

X1, X2

- Crystal Connection

BAT

- Battery Connection

DESCRIPTION

The DS1554 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) with a RTC
alarm, watchdog timer, power-on reset, battery monitor, and 32k x 8 non-volatile static RAM. User
access to all registers within the DS1554 is accomplished with a bytewide interface as shown in Figure 1.
The RTC Registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour
BCD format. Corrections for day of month and leap year are made automatically.

The RTC Registers are double-buffered into an internal and external set. The user has direct access to the
external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow
the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers are
continuously updated; this occurs regardless of external registers settings to guarantee that accurate RTC
information is always maintained.

DS1554

3 of 21

The DS1554 has interrupt (

IRQ

/FT) and reset (

RST

) outputs which can be used to control CPU activity.

The

IRQ

/FT interrupt output can be used to generate an external interrupt when the RTC Register values

match user programmed alarm values. The interrupt is always available while the device is powered from
the system supply and can be programmed to occur when in the battery backed state to serve as a system
wake-up. Either the

IRQ

/FT or

RST

outputs can also be used as a CPU watchdog timer, CPU activity is

monitored and an interrupt or reset output will be activated if the correct activity is not detected within
programmed limits. The DS1554 power-on reset can be used to detect a system power down or failure
and hold the CPU in a safe reset state until normal power returns and stabilizes; the

RST

output is used

for this function.

The DS1554 also contains its own power-fail circuitry which automatically deselects the device when the
V

supply enters an out of tolerance condition. This feature provides a high degree of data security

during unpredictable system operation brought on by low V

levels.

PACKAGES

The DS1554 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1554P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.

DS1554 BLOCK DIAGRAM Figure 1

DS1554

4 of 21

DS1554 OPERATING MODES Table 1

DQ0-DQ7

MODE

POWER

HIGH-Z

DESELECT

STANDBY

WRITE

ACTIVE

OUT

READ

ACTIVE

> V

HIGH-Z

READ

ACTIVE

< V

HIGH-Z

DESELECT

CMOS STANDBY

BAT

HIGH-Z

DATA

RETENTION

BATTERY

CURRENT

DATA READ MODE

The DS1554 is in the read mode whenever

(chip enable) is low and

(write enable) is high. The

device architecture allows ripple-through access to any valid address location. Valid data will be available
at the DQ pins within t

after the last address input is stable, providing that

and

access times are

satisfied. If

access times are not met, valid data will be available at the latter of chip enable

access (t

CEA

) or at output enable access time (t

OEA

). The state of the data input/output pins (DQ) is

controlled by

and

. If the outputs are activated before t

, the data lines are driven to an

intermediate state until t

. If the address inputs are changed while

and

remain valid, output data

will remain valid for output data hold time (t

) but will then go indeterminate until the next address

access.

DATA WRITE MODE

The DS1554 is in the write mode whenever

and

are in their active state. The start of a write is

referenced to the latter occurring transition of

. The addresses must be held valid throughout

the cycle.

and

must return inactive for a minimum of t

prior to the initiation of a subsequent

read or write cycle. Data in must be valid t

prior to the end of the write and remain valid for t

afterward. In a typical application, the

signal will be high during a write cycle. However,

can be

active provided that care is taken with the data bus to avoid bus contention. If

is low prior to

transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on

will then disable the outputs t

WEZ

after

goes active.

DATA RETENTION MODE

The 5-volt device is fully accessible and data can be written and read only when V

is greater than V

However, when V

is below the power-fail point V

(point at which write protection occurs) the

internal clock registers and SRAM are blocked from any access. When V

falls below the battery switch

point V

(battery supply level), device power is switched from the V

pin to the internal backup lithium

battery. RTC operation and SRAM data are maintained from the battery until V

is returned to nominal

levels.

The 3.3-volt device is fully accessible and data can be written and read only when V

is greater than

. When V

falls below V

, access to the device is inhibited. If V

is less than V

BAT

, the device

power is switched from V

to the internal backup lithium battery when V

drops below V

. If V

greater than V

BAT

, the device power is switched from V

to the internal backup lithium battery when

drops below V

BAT

. RTC operation and SRAM data are maintained from the battery until V

returned to nominal levels.

All control, data, and address signals must be powered down when V

is powered down.

DS1554

5 of 21

BATTERY LONGEVITY

The DS1554 has a lithium power source that is designed to provide energy for the clock activity, and
clock and RAM data retention when the V

supply is not present. The capability of this internal power

supply is sufficient to power the DS1554 continuously for the life of the equipment in which it is
installed. For specification purposes, the life expectancy is 10 years at 25

�

C with the internal clock

oscillator running in the absence of V

. Each DS1554 is shipped from Dallas Semiconductor with its

lithium energy source disconnected, guaranteeing full energy capacity. When V

is first applied at a

level greater than V

, the lithium energy source is enabled for battery backup operation. Actual life

expectancy of the DS1554 will be much longer than 10 years since no internal battery energy is
consumed when V

is present.

INTERNAL BATTERY MONITOR

The DS15543 constantly monitors the battery voltage of the internal batter. The Battery Low Flag (BLF)
bit of the Flags Register (B4 of 7FFF0h) is not writable and should always be a 0 when read. If a 1 is ever
present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are
questionable.

POWER-ON RESET

A temperature compensated comparator circuit monitors the level of V

. When V

falls to the power

fail trip point, the

RST

signal (open drain) is pulled low. When V

returns to nominal levels, the

RST

signal continues to be pulled low for a period of 40 ms to 200 ms. The power-on reset function is

independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.

CLOCK OPERATIONS

Table 2 and the following paragraphs describe the operation of RTC, alarm, and watchdog functions.

Электронный компонент: DS9034PCX